Continuous-time (CT) digital signal processing (DSP) has great potential, but can be constrained in its energy efficiency, because, for example, CT DSP systems may include a preceding continuous-time analog-to-digital encoder, which dissipates extra energy. Some prior art CT DSP systems implement level-crossing sampling (LCS) encoders, which can exhibit exponential worsening of CT DSP constraints, such as the number of output tokens produced per second by the encoder (NTPS) and the minimum time between two consecutive output encoder tokens (TGRAN), as the encoder resolution increases. Once the continuous-time encoder is selected, brute-force parallelization can be used to optimize the CT DSP. This has restricted prior art CT DSP systems to either low resolution or low bandwidth. A delay-based continuous-time analog-to-digital encoder can result in a low-supply implementation that can scale to provide high resolution. Therefore, there is a need for a delay-based continuous-time analog-to-digital encoder to address the problems identified in prior art CT DSP systems.